In computing, a cache is generally a hardware component that stores data so future requests for that data can be served faster. The data stored in a cache might be the result of an earlier computation, and/or the duplicate of data stored elsewhere. A cache hit occurs when requested data can be found in a cache, while a cache miss occurs when that requested data cannot be found in the cache. Cache hits are served by reading data from the cache, which is faster than reading the data from a slower data storage or memory. The more requests that can be served from the cache, the faster the system generally performs.
To be cost-effective and to enable efficient use of data, caches are relatively small. Nevertheless, caches have proven themselves in many areas of computing because typical computer applications tend to access data in recognizable patterns. These patterns typically exhibit a locality of reference (i.e. data requested in the future tends to be similar in some way to previously requested data). Some access patterns exhibit temporal locality, i.e. data may be requested again if it has been recently requested already. Other patterns exhibit spatial locality, which refers to requests for data that is physically stored close to data that has been already requested. Other forms of locality exist.
A cache replacement policy decides where in the cache a copy of a particular entry of data will go. If the replacement policy is free to choose any entry in the cache to hold the copy, the cache is called fully associative. At the other extreme, if each entry in main memory can go in just one place in the cache, the cache is direct mapped. Many caches implement a compromise in which each entry in main memory can go to any one of N places in the cache, and are described as N-way set associative. For example, the level-1 data cache in many processors is two-way or four-way set associative, which means that any particular location in main memory can be cached in either of two or four locations in the level-1 data cache.
Further, as with most memories, the cache only has so many ports by which data may be read from or written to. If more read/write accesses as scheduled to occur to a memory than there are read/write ports, then a conflict occurs and one or more of the data accesses must wait or be denied.